Hackaday · 68k-MBC, a 68008 computer in three chips
The ROM That Isn't There
Just4Fun's 68k-MBC runs a Motorola 68008 with only two other chips: a static RAM and a PIC microcontroller. There is no ROM. When the CPU comes out of reset and asks memory for its first instructions, the PIC answers instead, one byte per bus cycle. What it feeds the CPU are instructions to write the boot program into RAM, four bytes at a time. The CPU builds its own ROM.
Below is that boot, cycle by cycle, in the order the board's firmware expects. The program it loads here is my own, four bytes long.
68008the CPU, 8-bit data bus
PIC18F47Q10clock, I/O, and pretend ROM
SRAMthe only real memory
cycle 0–address –data –
Press Step to let the CPU out of reset.
| # | who | r/w | address | byte | what it is |
|---|
How the PIC gets away with it
The firmware calls this its single-step drive mode. Every bus cycle the CPU starts is held in a wait state until the PIC lets it finish. On a read, the PIC switches the RAM off, puts its own byte on the data bus, lets the cycle complete, then pulls HALT so the CPU pauses before the next one. On a write, it lets the CPU through to the RAM. A comment in the code notes that half a clock period of a 68008 at 8 MHz, 62.5 ns, is exactly one PIC instruction, so the delays are counted in NOPs.
The feed uses three instructions. MOVEA.L #addr,A0 sets a pointer, MOVE.L #data,(A0)+ writes four bytes there and moves the pointer on, and a final STOP parks the CPU. The firmware expects each move's four writes to come after the CPU has already fetched the next instruction word, and the log shows them that way. The CPU's address lines say it is reading instructions from $000400 upwards, but none of those reads reach the RAM. Only the writes do.
Then the PIC resets the CPU a second time. Now the reset vectors at addresses 0 to 7 really are in RAM, because the CPU put them there, and it boots on its own.
Sources: Hackaday, “2026 Retrocomputing Challenge: A Homebrew Computer In Only Three ICs”, 2 October 2026, for the three chips and the PIC acting as ROM. The 68k-MBC I/O subsystem firmware, IOS S310121-R220721 for the PIC18F47Q10, as published in github.com/rprouse/68K-MBC-IOS, for the feed sequence, the opcodes ($207C, $20FC, $4E72 with $2700), the reset values (stack $1000, start $400), the wait-state and HALT handling, the 62.5 ns note, and the CPU clock on the PIC's RC0 pin. The project page on hackaday.io was not reachable when I tried. The simulation is mine: it lists the bus cycles that sequence implies, not a trace from the board, and leaves out timing and simplifies the CPU's prefetch. Short programs are padded with zeros to a multiple of four bytes; the firmware itself warns that up to three “garbage” bytes can follow a loaded file. The four-byte program is MOVEQ #42,D0 ($702A) and BRA.S * ($60FE): put 42 in a register, then loop forever. Made by Claude, 3 October 2026.